FPGA Engineer
US-IA-Iowa (Remote Employees)
Job Description:
• Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and
system integration
• Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
• Contribute to engineering estimates for new program pursuits.
• May provide technical leadership for project design teams by breaking down work, planning activities, and
reporting status
Must have Skills:
• RTL coding and simulation in VHDL/Veriog
• Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
• Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or
other FPGA-specific tools)
• Git, Subversion
• Experience with Unix, scripting, C/C++, and/or Perl
Preferred Skills:
• Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random,
functional coverage, SystemVerilog)
• ASIC / FPGA lab validation with advanced lab equipment
• Design for Test (DFT) and manufacturability issues
• Experience with Unix, scripting, C/C++, and/or Perl
Any special or skills related notes:
Ability to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix
into projects with aggressive schedules and frequent milestones
Strong oral and written communication skills with the ability to document and present one's work and status
Education:
• Bachelor's of engineering
Work Arrangement Fully On-Site: Must be able to travel to an Arrow Client office location as requested by
Arrow
Client leadership.
Location: Cedar Rapids, IA (Day-1 Onsite)
Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.
Location:US-IA-Iowa (Remote Employees)
Time Type:Full time
Job Category:Engineering ServicesEEO Statement:
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)
We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.
Job Profile
May be required to be present at designated office Must travel to client office as requested Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes
Benefits/Perks Tasks- Asic/fpga design
- Continuous Improvement
- Integration
- Requirements capture
- System integration
- Technical Leadership
ASIC Asic simulation tools C C++ Chip-level verification Communication Design for test Digital circuit architecture Engineering Services FPGA Fpga simulation tools Git Integration Leadership Modelsim Perl Quartus Reporting Rtl coding Scripting Services Subversion Synplify SystemVerilog Technical Leadership Test Timing analysis Timing closure UNIX Validation Verification Verilog VHDL Vivado
EducationBachelor's of engineering BE Engineering
TimezonesAmerica/Anchorage America/Chicago America/Denver America/Los_Angeles America/New_York Pacific/Honolulu UTC-10 UTC-5 UTC-6 UTC-7 UTC-8 UTC-9