FreshRemote.Work

Silicon Digital Design Engineer

United States - Remote

Fresh Consulting is a design-led, software development and hardware engineering company, offering end-to-end digital services to help companies innovate.  We bring together amazing UX designers, sophisticated developers, digital strategists, and top-notch engineers to help companies create fresh experiences that connect humans, systems, and machines.  We’ve been growing fast and need someone to help us continue managing high-quality work delivery in a fast-paced environment. 

See more at freshconsulting.com Visit freshconsulting.com/portfolio to see our project work across several industries.

View and apply to all jobs - https://freshconsulting.applytojob.com/apply/ or visit freshconsulting.com/careers


Title: Silicon Digital Design Engineer
Duration: 1 year with possible extension 
Location: Remote. Must live and work in AZ or CA or CO or FL or GA or IL or IN or MN or NY or NC or OR or TX or UT or WA
Benefits: Employee benefits at 100% including Medical, PTO, Holiday Pay, 401K Plan and much more!
Hours: Minimum 40 Hours/Week 

Role:
- Own ASIC IP RTL implementation for IP blocks.
- Ensure RTL written meets quality checks like Lint/CDC/RDC.
- Collaborate closely with design team members, technical leads, and the architecture team to ensure the block meets the power and performance requirements.
- Collaborate closely with the verification team to develop test plans and review test coverage.
- Perform IP integration.
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
- Work with FPGA engineers to perform early prototyping
- Support hand-off and integration of blocks into larger SOC environments
- Assist with Algorithm analysis.

Skills:
- 4+ years of experience as a Digital Design Engineer.
- Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC.
- Experience having worked on a design from scratch – code from the ground up (outline/provide project work, if available)
- Experience in RTL coding and coding for low power in ASICs.
- Experience in digital design µArchitecture.
- Familiarity with Verilog and SystemVerilog coding.
- Perl, Tcl, and Python (or similar) scripting experience

Education: BS in Electrical Engineering/Computer Science/Computer Engineering or equivalent experience


FRESH--
- Work on engineering and research assignments with F500 companies and startups.   
- The relationships that we have created with our clients are one of a kind.    
- We help solve problems in many technologies focusing on R&D, product development, and manufacturing.    
- We work with the most cutting-edge and latest technologies from AR/VR to Autonomous technologies.    
- Closely working with our clients, we believe that long-term investments are significant to maintain the culture we have created together.

We’re a handpicked team of Engineers, digital strategist, designers, and developers united together in creating a fresh experience. Whether we are strategizing, designing, developing, or analyzing, our integrated team works as an extension of yours to improve your impact, your usability, and your customer conversion. In the process, we collaborate with you to get to know your business, understand your industry, and incorporate your big ideas into memorable experiences that keep your customers coming back for more.

Equal employment opportunity: All qualified persons will be considered for employment without regard to race, color, religion, sex, national origin, age, marital status, familial status, gender identity, sexual orientation, disability for which a reasonable accommodation can be made or any other status protected by law.  Assistance will be gladly provided upon request for any applicant with sensory or non-sensory disabilities.

Fresh Consulting is a participating E-Verify company.

freshconsulting.com

Compensation offered will be determined by factors such as location, level, job-related knowledge, skills, and experience. Range $70/hr - $80/hr. Apply

Job Profile

Regions

North America

Countries

United States

Restrictions

CA CO FL GA IL IN MN Must live and work in AZ NC NY OR TX UT WA

Benefits/Perks

401(k) Plan Holiday Pay Medical PTO

Tasks
  • Assist with Algorithm analysis
  • Collaborate with design and verification teams
  • Ensure quality checks
  • Own ASIC IP RTL implementation
  • Perform IP integration
  • Supervise RTL-to-GDS flow
  • Support hand-off and integration of blocks
Skills

ASIC Digital Design Perl Python RTL Coding SystemVerilog TCL Verilog

Experience

4+ years

Education

BS in Electrical Engineering Computer Engineering Computer Science

Timezones

America/Anchorage America/Chicago America/Denver America/Los_Angeles America/New_York Pacific/Honolulu UTC-10 UTC-5 UTC-6 UTC-7 UTC-8 UTC-9