ASIC Engineer, Formal Verification
Sunnyvale, CA | Austin, TX | Remote, US
- Provide technical leadership in Formal Verification
- Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level
- Work with Architecture and Design team to come up with Formal driven specification and implementation
- Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level
- Build reusable/scalable environments for Formal Verification and deploying the tools
- Evaluate and recommend EDA solutions for Formal Verification
- Provide training for internal teams and mentoring engineers related to Formal Verification Technology
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 5+ years of experience in Formal Verification
- Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
- Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques
- Proven analytical skills to craft novel solutions to tackle industry-level complex designs
- Demonstrated experience with effective collaboration with cross functional teams
- Fluency in hardware description languages, such as SystemVerilog and SVA
- Proficiency in scripting languages such as Python, Perl, or Tcl
- Experience with JasperGold or VC-Formal
- Experience to quickly understand and interpret specifications and extract design behaviors/properties
- Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW accelerators
- Experience with complex SoCs
- Formal verification experience in clock domain crossing, IP-XACT based register verification and low power
- Experience with development of fully automated flows from specification to fully verified designs
- Experience with simulators and waveform debugging tools
$१,७३,०००/year to $२,४९,०००/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
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Job Profile
Must be located in California for this position
Benefits/PerksAccommodations Benefits Bonus Comprehensive benefits Equity Individual compensation Reasonable accommodations
Tasks- Build
- Collaborate with cross functional teams
- Debugging
- Design
- Develop formal test plans
- Implement formal verification methodology
- Provide technical leadership
- Provide training
- Train and mentor engineers
Analytical Architecture ASIC Design Collaboration Computer Engineering Computer Science Data center Debugging Debugging Tools Design Developing EDA solutions Emulation Engineering Formal Verification GPU Identity Infrastructure JasperGold Leadership Mentoring Methodologies Organization Perl Physics Procedures Python Scripting Scripting Languages SVA SystemVerilog TCL Technical Technical Leadership Techniques Tools VC-Formal Virtual reality
Experience5 years
EducationBachelor Bachelor's Bachelor's degree Bachelor’s degree in Computer Engineering Bachelor's degree in Computer Science Computer Engineering Computer Science Design Engineering Equivalent Equivalent practical experience Physics Relevant technical field Technical field Technology
TimezonesAmerica/Anchorage America/Chicago America/Denver America/Los_Angeles America/New_York Pacific/Honolulu UTC-10 UTC-5 UTC-6 UTC-7 UTC-8 UTC-9